The present invention relates to customizable circuitry, and particularly to customizable circuitry which includes an interconnect for receiving and electrically connecting electrical devices and tape automated bonding chip designs. The invention relates to an interconnect which can be produced in gross with an undedicated, universal structure and subsequently customized to a specific application with minimal effort and fabrication, and to a tape automated bonding chip design for use therewith. Further, the invention also concerns a method for manufacturing the interconnect and chip design.
Customizable circuitry, as used herein, refers to that circuitry in which some of the device interconnections are not made during the initial manufacture of the circuitry, but are deferred. This deferral allows the circuitry to be manufactured in large quantities with generic properties, with the specific design details being applied later by the user in a final step called "customization." Integral to customizable circuitry is a generic interconnect structure coupled with a method of bonding the leads of integrated circuit chips to that interconnect structure.
Interconnects, as building blocks for electronic circuitry and microcircuitry, typically receive and support further electrical devices, for example, substrates, i.e., smaller scale interconnects, integrated chips, capacitors, resistors and so forth, which can be electrically connected to one another to provide larger, more complex electrical structures. The interconnects typically have a sandwich-type structure through which a series of wires extend. The wires connect the electrical devices attached to the interconnect according to a plan specified by the interconnect user.
The interconnects are used in a multiplicity of designs, each requiring unique electrical circuitry. Presently, in a majority of the interconnects, the wiring plan is fixed at an early stage of manufacture. In other words, the manufacturer lays down the interconnect wiring according to a specific, predetermined plan. Such interconnects will be referred to as "design specific." As is readily apparent, design specific interconnects cannot be mass produced and are, therefore, time and cost intensive.
Recognizing the shortcomings of design-specific interconnects, there arose a need in the interconnect industry for an interconnect design which could be mass-produced in an unspecified manner and thereafter programmed to produce whatever wiring plan is required by the user. Such interconnects will be referred to as "programmable interconnects" and the final step of imposing the wiring plan on the interconnect will be referred to as "customization."
It is desirable, though, to retain some of the benefits of design-specific interconnects. For example, design-specific interconnects can be designed to minimize transmission line signal reflection or ringing effects. Interconnect transmission line effects are becoming increasingly important as integrated chip performance improves. Traditionally, large discrete series or shunt resistors have been added to interconnects in order to address undesirable signal reflection or ringing effects. However, adding discrete resistors increases manufacturing complexity and costs while consuming more circuit space. Therefore, alternative methods to address deleterious transmission line effects are desirable.
As disclosed in U.S. Pat. No. 4,210,885 to Ho, judiciously selecting the resistance value for each interconnect route relative to the characteristic impedance of the associated transmission line will minimize reflection or ringing problems. The Ho circuit adjusts the resistance without adding discrete resistors by distributing the resistance into the interconnect route itself. A specific resistance may be achieved by varying interconnect wire geometries and the characteristic resistance of the interconnect material. It is desirable that the resistance in the interconnect route be large enough to substantially reduce the signal reflection or ringing, yet at the same time not be so large as to severely attenuate the signal. For high frequency signals, a satisfactory reduction in signal reflection has been found when interconnect route resistance, R.sub.I, is within a general range of 2/3 Z.sub.0 .ltoreq.R.sub.I .gtoreq.2 Z.sub.0, where Z.sub.0 is the characteristic impedance of the transmission line seen by the signal source.
A previous attempt at programmable interconnect design is disclosed in U.S. Pat. No. 4,458,297 to Mosaic Systems, Inc. The Mosaic design provides interconnect wiring in the form of a grid with wires in one direction forming one plane and orthogonal wires forming a second plane. Positioned between the two sets of wires is a layer of amorphous silicon which, though originally non-conductive, can be rendered conductive at specified points of wire overlap. The selective conductivity is achieved through crystallization of the amorphous silicon by applying a voltage differential across the orthogonal wires. The electric field produced by this voltage differential causes the silicon in the region of the overlapped wires to crystallize and become conductive. Therefore, an electrical path is formed between the overlapped wires.
The Mosaic structure is advantageous in that it provides for the mass production of undedicated interconnects which can be customized by the manufacturer or by the end user at a later stage of manufacture. The Mosaic interconnect, however, has many drawbacks. For example, because of the electrical properties required, a limited number of materials can be used. Amorphous silicon is the only suggested material for use as the intermediate layer. Also, while a limited number of metals might be used for the interconnect wiring, aluminum is by far the best candidate because its properties are compatible with the amorphous silicon. The density of the Mosaic grid, and specifically the proximity of the wires in the overlap region, is limited since a sufficiently large area about the overlap region is required to avoid shorting of adjacent wires during crystallization. In other words, the electric field forms an area of flux between the overlapped wires extending into the area between adjacent overlap regions. If the wires are placed too close together, this region of flux may cause adjacent regions to bleed together and short the adjacent wires.
Another disadvantage of the Mosaic design is that it is only an additive process. In other words, the wire routing is formed by adding electrically conductive segments, i.e., the crystalline silicon bridges. The design is not subtractive. Accordingly, it is very difficult, if not impossible, to make changes to the customized interconnect. The difficulty in altering the customized wiring makes engineering changes impractical. A further and very crucial disadvantage in the Mosaic design results from the fact that each additive step, i.e., creation of the silicon bridge, excludes both affected orthogonal wires from further utilization in the interconnect plan, except as to this one route. In other words, if X1 and Y1 wires are bridged to provide an interconnect path, these wires, or segments thereof, cannot be used to provide another interconnect path, for to do so would result in a shorting of the two paths together. This characteristic of the Mosaic interconnect severely limits the complexity of the interconnect for a given interconnect area. This complexity limit affects the interconnect efficiency for the available channels, called channel utilization. It is desirable to have high channel utilization since a given interconnect can be performed with fewer channels if high channel utilization is present.
Furthermore, the Mosaic design does not address transmission line ringing or reflection. In general, line resistance matching methods such as disclosed by Ho have not been available in programmable designs because final interconnect wire lengths design are not known until after customization.
Other electrically programmable interconnect designs are known to those skilled in the art. For example, capacitor like structures may be used as a programmable element for connecting interconnect lines by utilizing the dielectric breakdown properties of the structures. The capacitor like structure can be formed between interconnect lines such that the structure has low leakage current in an unprogrammed state. The structure has a dielectric layer between two conductive layers and after applying a high electric field to the structure the dielectric material electrically breaks down and a conductive path between the interconnect lines is created. Such a structure is sometimes called an anti-fuse because unlike a typical electrical fuse, which is originally conductive then electrically blown, an anti-fuse is normally nonconductive then electrically switched to a conductive state. Such capacitor like structures are disclosed in U.S. Pat. No. 4,899,205 to Hamdy et al. and U.S. Pat. No. 4,823,181 to Mohsen, the disclosure of these two patents is expressly incorporated herein by reference. Various electric circuits can be used to electrically address and incorporate such anti-fuse programmable elements. These circuits include those disclosed in U.S. Pat. No. 4,857,774 to El-Ayat et al. and U.S. Pat. No. 4,758,745 to Elgamal et al., the disclosure of these two patents is expressly incorporated herein by reference.
Additional methods for using electrically programmable elements in interconnects exists including, but not limited to, pass transistors, diode arrangements and standard fuse arrangements. For example, transistors may be placed between the interconnect lines. In order to electrically connect or disconnect two lines, a pass transistor connecting the lines is turned on or off. U.S. Pat. No. 4,870,302 to Freeman, U.S. Pat. No. 4,855,619 to Hsieh et al., and U.S. Pat. No. 4,642,487 to Carter disclose the use of transistors to connect interconnect lines, the disclosure of these three patents is expressly incorporated herein by reference. The use of diodes as programmable elements is also known and is disclosed in U.S. Pat. No. 4,876,220 to Hamdy et al., the disclosure of which is expressly incorporated herein by reference.
The various electrical programmable elements described above, however, do not incorporate the use of full universal customizable circuits, but rather are used in design specific interconnects. It is desirable to incorporate electrical programming capabilities in a generic universal customizable circuit.
In addition to electrical customization approaches, mechanical customization has also been used in some areas. For example, "Wire-Wrap" involves the use of an interconnect having a number of metal pins extending orthogonally from the interconnect surface. After the wiring plan has been specified, the appropriate pins can be connected by wrapping wires about the appropriate pins. Because of the forces involved, large, rigid pins are needed along with large tools to wrap the wire securely. The process is time consuming, since only one wire is added at a time, and cannot be used for small scale circuits such as integrated circuits because of the large pins and tools required.
Another mechanical customization approach is the use of wire bonding to interconnect bonding pads provided on the surface of an integrated circuit. The interconnect is provided by welding or sputtering a thin wire onto a metal bonding pad at each end of the desired interconnect path. This approach has many disadvantages, however, including very poor area efficiency. For example, the sputtering used requires the use of large bonding pads with large spaces between them to assure that the sputtering process does not destroy the pad or cause a short circuit. Further, because the interconnect wires are not insulated, the density is restricted to those interconnect paths that do not require crossed wires. Thus, this procedure has most of the disadvantages of wire wrap with the additional disadvantage that interconnect paths cannot cross each other. In addition, both wire-wrap and bond pad methods fail to provide simple means to minimize undesirable transmission line effects without using additional components and adding to the interconnect complexity.
Turning now to the problems of mounting the integrated circuit chips, it is conventional practice to mount such chips on interconnect structures which serve to electrically connect the chips. The integrated circuit chips are frequently mounted on carrier film, or tape, by a process known as "Tape Automated Bonding" (TAB). To achieve efficiency in the resulting customizable circuit, it is important to match the chip bonding technique used to the particular interconnect structure.
Accordingly, there exists a need in the art for an improved customizable circuitry including a programmable interconnect which can be mass produced to include an unspecified wiring plan and which can be subsequently specified in the later stages of manufacture or by the end-user with a minimum of effort and time, and which can provide a dense interconnect structure which can be practiced at both the printed circuit and integrated circuit levels, and a tape automated bonding structure compatible with such interconnects. Furthermore, there exists a need in the art for an improved customizable circuitry that also substantially reduces undesirable transmission line effects without increasing space requirements and adding to manufacturing complexity.